
module assert_encoder(
clk,
rst_n,
polar_enc_start,
polar_enc_done,

polar_enc_data_in,
polar_rate_sel,
polar_enc_data_out
);
input clk;
input rst_n;
input polar_enc_start;
input polar_enc_done;

input [384 - 1 : 0] polar_enc_data_in;
input polar_rate_sel;
input [1024 - 1 : 0] polar_enc_data_out;

always@(posedge clk)
begin
    assert(rst_n || (!polar_enc_start));
end



endmodule